1. Field of the Invention
The present invention relates to a ferroelectric memory, and more particularly, it relates to a ferroelectric memory having a ferroelectric capacitor.
2. Description of the Background Art
A ferroelectric memory has recently been watched with interest as a high-speed nonvolatile memory requiring low power consumption. Therefore, the ferroelectric memory is subjected to active research and development.
FIG. 11 is a representative circuit diagram of a most generally employed conventional 1T1C ferroelectric memory, and FIG. 12 is a sectional view corresponding to FIG. 11. Referring to FIGS. 11 and 12, element isolation regions 102 are formed on prescribed regions of the surface of a semiconductor substrate 101 in the structure of this conventional 1T1C ferroelectric memory. Source regions 103 and a drain region 104 are formed at prescribed intervals on an element forming region enclosed with the element isolation regions 102. Gate electrodes 106 constituting word lines WL are formed on channel regions located between the source regions 103 and the drain region 104 through gate insulator films 105. Each bit line (BL) 113 is electrically connected to the drain region 104.
Lower electrodes 109 are connected to the source regions 103 through plug electrodes 108. Upper electrodes 111 forming plate lines PL are formed on the lower electrodes 109 through ferroelectric films 110. The lower electrodes 109, the ferroelectric films 110 and the upper electrodes 111 constitute ferroelectric capacitors 112. The source regions 103 and the drain region 104, the gate insulator films 105 and the gate electrodes 106 constitute transistors 107. These transistors 107 function as switches for selecting memory cells 100. As shown in FIG. 11, each memory cell 100 is constituted of a single transistor 107 and a single ferroelectric capacitor 112. A memory having this memory cell structure is referred to as a 1T1C ferroelectric memory. The 1T1C ferroelectric memory, having a structure obtained by replacing storage capacitors with ferroelectric capacitors in a DRAM, allows utilization of a conventional DRAM design technique.
A simple matrix ferroelectric memory having memory cells each constituted of only a single ferroelectric capacitor is also developed in general. FIG. 13 is a circuit diagram of a conventional simple matrix ferroelectric memory, and FIG. 14 is a sectional view corresponding to FIG. 13. Referring to FIGS. 13 and 14, a ferroelectric film 202 is formed on each bit line (BL) 201. Each word line (WL) 203 is formed on the ferroelectric film 202 to intersect with the bit line 201. The bit line 201, the ferroelectric film 202 and the word line 203 constitute a ferroelectric capacitor 210. In the simple matrix ferroelectric memory, each memory cell 200 is constituted of only a single ferroelectric capacitor 210, as shown in FIG. 13. Therefore, the memory cells 200 can be reduced in size and highly integrated.
In data reading, however, each of the aforementioned 1T1C and simple matrix ferroelectric memories generally requires polarization inversion of changing the polarization direction of each ferroelectric film. Repetition of such polarization inversion disadvantageously results in polarization fatigue/deterioration such as reduction of remanence.
In general, therefore, an FET ferroelectric memory having a reading method causing no polarization inversion is developed. For example, Japanese Patent Laying-Open No. 2002-251877 discloses such an FET ferroelectric memory.
Also known as an FET ferroelectric memory is an MFIS-FET (metal ferroelectric insulator semiconductor-field effect transistor) ferroelectric memory or an MFMIS-FET (metal ferroelectric metal insulator semiconductor-field effect transistor) ferroelectric memory having ferroelectric capacitors formed on gate portions of transistors.
FIG. 15 is a circuit diagram showing a conventional one-transistor (FET) ferroelectric memory having memory cells formed by MFMIS-FETs, and FIG. 16 is a sectional view corresponding to FIG. 15. Referring to FIGS. 15 and 16, a well region 302 is formed on the surface of a semiconductor substrate 301 in this FET ferroelectric memory. Source regions 303 and a drain region 304 are formed on the surface of the well region 302 at prescribed intervals. Gate electrodes 306 are formed on channel regions located between the source regions 303 and the drain regions 304 through gate insulator films 305.
Word lines (WL) 308 are formed on the gate electrodes 306 through ferroelectric films 307. Each bit line (BL) 310 is electrically connected to the drain region 304. Plate lines (PL) 311 are connected to the source regions 303. Each source line (SL) 312 is connected to the well region 302. The gate electrodes 306, the ferroelectric films 307 and the word lines 308 constitute one-transistor ferroelectric capacitors 315. The source regions 303 and the drain region 304, the gate insulator films 305 and the gate electrodes 306 constitute transistors 309. In this case, each memory cell 300 has a structure obtained by forming a single ferroelectric capacitor 315 on a gate portion of a single transistor 309.
The aforementioned Japanese Patent Laying-Open No. 2002-251877 disclosing the FET ferroelectric memory proposes a reading method causing no polarization inversion utilizing the difference between electric capacitances resulting from different polarization states.
However, the aforementioned Japanese Patent Laying-Open No. 2002-251877 disclosing the FET ferroelectric memory discloses no method of increasing a read margin by increasing signal potential difference at the time of reading information of stored data “0” or “1”. Therefore, the signal potential difference at the time of reading the information of the data “0” or “1” may be less than the minimum readable signal potential difference. This disadvantageously results in false data reading or the like.